1. Field of the Invention
The present invention relates to a semiconductor device provided with a region for isolation between semiconductor elements, particularly a isolation region given by an insulator or dielectric material.
2. Description of the Related Arts
Conventionally, there is a dielectric isolation method given by a trench in a bipolar integrated circuit integrating bipolar transistors. In this method, a dielectric isolation portion is given by a capacitor structure in construction. Thus, interference between circuits often becomes an issue. Accordingly, there is offered a method in which conductive material is buried in a trench so as to fix an electric potential of constant thereby to prevent capacitive coupling and to prevent interference between circuits (for instance, Japanese Patent Publication leid open No. 3-148852).
Incidentally, for an isolation region in the trench portion flatness of an upper portion of the trench must be originally ensured. However, an electrode drawing portion becomes necessary because a contact may not be directly formed on the buried conductive material in the trench. Thus, it is difficult to ensure the flatness. In addition, it is considered to form the trench portion widely. However, it takes an hour to fully bury the trench portion with conductive material. It is undesirable that a surplus amount of conductive material accumulated on the semiconductor substrate also increased to facilitate lowering of flatness of the trench upper portion more and more and to increase etching time. Furthermore, it has been required to increase masking process for forming a contact on the buried conductive material.